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| A-Data Synchronous DRAM General Description The ADS4616A4A are two-bank Synchronous DRAMs organized as 524,288 words x 16 bits x 2 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications ADS4616A4A 512K x 16 Bit x 2 Banks Features *Single 3.3V +/- 0.3V power supply *MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8, & full page) -Burst Type (sequential & Interleave) *2 banks operation *All inputs are sampled at the positive edge of the system clock *Burst Read single write operation *Auto & Self refresh *4096 refresh cycle *DQM for masking *Package:50-pins 400 mil TSOP-Type II Ordering Information. Part No. ADS4616A4A-5 ADS4616A4A -6 ADS4616A4A -7 Frequency 200Mhz 166Mhz 143Mhz Interface LVTTL LVTTL LVTTL Package 400mil 50pin TSOPII 400mil 50pin TSOPII 400mil 50pin TSOPII Pin Assignment VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM /WE /CAS /RAS /CS (BS)A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Vss DQ15 DQ14 VssQ DQ13 DQ12 VDD Q DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS 50-pin plastic TSOP II 400 mil Rev 1 December, 2001 1 A-Data Pin Description PIN CLK CKE NAME System Clock Clock Enable FUNCTION Active on the positive edge to sample all inputs. ADS4616A4A Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input except CLK, CKE and L(U)DQM A0~A10 Address Row / Column address are multiplexed on the same pins. Row address : A0~A10 Column address : A0~A7 DQ0~DQ15 Data L(U)DQM Data Mask /RAS /CAS /WE Row Address Strobe Column Address Strobe Write Enable Data inputs / outputs are multiplexed on the same pins. Makes data output Hi-Z, Latches row addresses on the positive edge of the CLK with /RAS low Latches Column addresses on the positive edge of the CLK with /CAS low Enables write operation and row recharge. Power and Ground for the input buffers and the core logic. Power supply for output buffers. This pin is recommended to be left No Connection on the device. VDD/VSS Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground NC No Connection Block Diagram CLK CKE Address Clock Generator Bank B Row Decoder Mode Register Address Buffer & Refresh Counter Bank A Amplifier DQM Command Decoder /RAS /CAS /WE Control Logic /CS Input & Output Buffer Data Latch Column Address Buffer & Refresh Counter Column Decoder Data Control Circuit DQ Rev 1 December, 2001 2 A-Data Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, Vout VDD, VDDQ TSTG PD IOS Value -0.3~ 4.6 -0.3~ 4.6 -55 ~ +150 1 50 ADS4616A4A Unit V V W mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD, VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 Max 3.6 VDD+0.3 0.8 0.4 5 5 Unit V V V V V uA uA 1 2 IOH=-2mA IOL=2mA 3 4 Note Note : 1. VIH (max)=VDDH+2.0V with a pulse width < 3ns 2.VIL(min)=VSSQ-2.0V with a pulse < 3ns and - 1.5V with a pulse < 5ns 3.Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V VOUT VDD. AC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter AC input high / low level voltage Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement Symbol VIH / VIL Vtrip TR / tF Voutfef CL Value 1.4 / 1.4 1.4 1 1.4 50 Unit V V ns V pF Note Rev 1 December, 2001 3 A-Data Capacitance TA=25, f-=1Mhz, VDD=3.3V Parameter Input capacitance CLK A0~A11,BA0,BA1,CKE,/CS,/RAS, /CAS,/WE,DQM Data input / output capacitance DQM CI/O 4 Pin Symbol C11 C12 Min 2.5 2.5 ADS4616A4A Max 4 5 Unit pF pF 6.5 pF Output load circuit 1.4 V 50 ohms Output Z= 50 ohms 30 pF DC Characteristics I Parameter Input leakage current Output leakage current Output high voltage Output low voltage ILI ILO VOH VOL Symbol Min -5 -5 2.4 Max 5 5 0.4 Unit uA uA V V Note 1 2 IOH = -2mA IOL = 2mA Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V. 2.DOUT is disabled, VOUT = 0 to 3.6. Rev 1 December, 2001 4 A-Data DC Characteristics II Speed Parameter Symbol Test condition -5 Burst length=1, One bank active Operating Current Precharge standby current in power down mode IDD2PS CKEVIL(max), tCK= CKEVIH(min), /CSVIH(min), tCK=min input signals are Precharge standby current in Non power down mode IDD2NS Input signals are stable. Active standby current in power down mode CKEVIH(min), /CSVIH(min), Active standby current in Non power IDD3N down mode tCK=min input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V Burst mode operating IDD4 current Auto refresh current Self refresh current IDD5 active IDD6 CKE0.2V 200 All banks active tRRCtRRC(min), All banks 60 55 tCKtCK(min),IOL=0 mA 120 110 3 IDD3P CKEVIL(max), tCK=min 45 40 IDD2N changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKEVIH(min), tCK= 8 35 30 1 IDD1 tRCtRC(min),IOL=0mA CKEVIL(max), tCK=min 70 60 -6 ADS4616A4A Unit -7 50 mA Note 1 IDD2P 1 mA 25 mA 35 mA mA 100 mA 1 50 mA uA 2 Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics. Rev 1 December, 2001 5 A-Data AC Characteristics -5 Parameter System clock /CAS Latency = 3 Cycle time /CAS Latency = 2 Symbol Min tCK3 tCK2 tCHW tCLW tAC3 tAC2 tRC tRCD tRAS tRP tRRD tCCD tOH tDS tDH tAS tAH tPDE tREF 5 1000 7 2 2 54 14 40 14 10 1 1.5 1.5 1 1.5 1 5 4.5 4.5 100K 64 8 2 2 60 18 42 18 12 1 2 1.5 1 1.5 1 5 5 5.5 100K 64 Clock high pulse width Clock low pulse width Access time form clock Row cycle time /RAS to /CAS delay /RAS active time /RAS precharge time /RAS to /RAS bank active delay /CAS to /CAS delay Data - out hold time Data - input setup time Data - input hold time Address setup time Address hold time Power down exit time Refresh time /CAS Latency = 3 /CAS Latency = 2 Max Min 6 1000 10 2 2 65 20 45 20 14 1 2.5 1.5 1 1.5 1 5 5 ns 5.5 100K 64 ns ns ns ns ns CLK ns ns ns ns ns CLK ms 1 1 1 1 2 ns ns 1 1 Max Min 7 1000 ns Max -6 -7 Unit Note ADS4616A4A Note : 1. Assume tR / tF (input rise and fall time) is 1 ns. 2. Access times to be measured with input signals of 1v / ns edge rate. 3.A new command can be given tRRC after self refresh exit. Rev 1 December, 2001 6 A-Data Command Truth-Table Command Mode Register Set No Operation Bank Active Read H Read with Auto Precharge Write Write with Auto Precharge Precharge All Bank H Precharge select Bank Burst Stop DQM Entry Self Refresh Exit L H L Entry Precharge Power down Exit L H X H L H X H H H H H L L H X L H X L X L X H X H L X L L H L L H X L H L L X L H L H CKEn-1 H H H CKEn X X X /CS L L L /RAS L H L /CAS L H H /WE L H H L H L H H A10 X X ADS4616A4A A9-A0 V X V V V X X X X X X Entry Clock Suspend Exit H L L L X X X Rev 1 December, 2001 7 A-Data Package Information 50 26 ADS4616A4A 25 SYMBOL A A1 A2 B c D HE E e L L1 MIN. 0.05 0.95 0.30 0.12 11.56 10.03 0.80 BSC 0.40 MILLIMETER NOM. 0.10 1.00 21.08 BSC 11.76 10.16 0.50 0.80 REF 0.71 REF - MAX. 1.20 0.15 1.05 0.45 0.21 11.96 10.29 0.60 MIN. 0.002 0.037 0.012 0.005 0.460 0.395 0.0315 0.016 INCH NOM. 0.039 0.830 BSC 0.463 0.400 0.020 0.031 REF 0.028 REF - MAX. 0.047 0.006 0.041 0.018 0.008 0.471 0.405 0.024 S 0 5 0 5 400mil 50pin TSOP II Package Rev 1 December, 2001 8 |
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